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cy7c024e/cy7c0241e cy7c025e/cy7c0251e 4 k 16/18 and 8 k 16/18 dual-port static ram with sem, int, busy cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-62932 rev. *e revised august 13, 2013 features true dual-ported memory cells that allow simultaneous reads of the same memory location 4 k 16 organization (cy7c024e) 4 k 18 organization (cy7c0241e) 8 k 16 organization (cy7c025e) 8 k 18 organization (cy7c0251e) 0.35- complementary metal ox ide semiconductor (cmos) for optimum speed and power high-speed access: 15 ns low operating power: i cc = 180 ma (typ), i sb3 = 0.05 ma (typ) fully asynchronous operation automatic power-down expandable data bus to 32/36 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to-port communication separate upper-byte and lower-byte control pin select for master or slave available in pb-free 100-pin thin quad flatpack (tqfp) package functional description the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e are low-power cmos 4k 16/18 and 8k 16/18 dual-port static rams. various arbitration schemes are included on the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e can be used as standalone 16 or 18-bit dual-port static rams or mult iple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static ram. an m/s pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multipro cessor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semap hore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power-down feature is controlled independently on each port by a ce pin. the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e are available in 100-pin pb-free tqfp. selection guide parameter ?15 ?25 ?55 maximum access time (ns) 15 25 55 typical operating current (ma) 190 170 150 typical standby current for i sb1 (ma) 50 40 20
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 2 of 23 logic block diagram l l l oe l a 0l r/w r ub r ce r oe r ce l oe l ub l ub r i/o 8l ?i/o 15l interrupt semaphore arbitration control i/o memory array address decoder sem l sem r busy l int l int r m/s control i/o lb l lb r i/o 0l ? i/o 7l r/w l r/w r lb r ce r oe r a 0r i/o 8r i/o 15r busy r i/o 0r i/o 7r (cy7c025e/0251e) a 12l a 12r (cy7c025e/0251e) [6] [1] ? ? address decoder a 11l a 11r [9] [10] [2] [3] r/w ub lb ce l notes 1. busy is an output in master mode and an input in slave mode. 2. i/o 0 ?i/o 8 on the cy7c0241e/cy7c0251e. 3. i/o 9 ?i/o 17 on the cy7c0241e/cy7c0251e.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 3 of 23 contents pin configurations ........................................................... 4 pin definitions .................................................................. 5 architecture ...................................................................... 6 functional description ..................................................... 6 write operation ........................................................... 6 read operation ........................................................... 6 interrupts ..................................................................... 6 busy ............................................................................ 6 master/slave ............................................................... 6 semaphore operation ............ .............. .............. ......... 6 maximum ratings ............................................................. 9 operating range ............................................................... 9 electrical characteristics ................................................. 9 capacitance .................................................................... 10 data retention mode ...................................................... 10 data retention timing ................................................... 10 switching characteristics .............................................. 11 switching waveforms .................................................... 13 ordering information ..................................................... 19 4 k 16 dual-port sram ......................................... 19 8 k 16 dual-port sram ......................................... 19 4 k 18 dual-port sram ......................................... 19 8 k 18 dual-port sram ......................................... 19 ordering code definitions ..... .................................... 19 package diagrams .......................................................... 20 acronyms ........................................................................ 21 document conventions ................................................. 21 units of measure ....................................................... 21 document history page ................................................. 22 sales, solutions, and legal information ...................... 23 worldwide sales and design s upport ......... .............. 23 products .................................................................... 23 psoc? solutions ...................................................... 23 cypress developer community ................................. 23 technical support ................. .................................... 23
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 4 of 23 pin configurations figure 1. 100-pin tqfp (top view) 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc nc nc i/o 10l i/o 11l i/o 15l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 14l gnd i/o 12l i/o 13l a 1r a 2r a 3r a 4r nc nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 8l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 8r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r ? r r/w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c024e/cy7c025e r/w l [4] [5] notes 4. a 12l on the cy7c025e/cy7c0251e. 5. a 12r on the cy7c025e/cy7c0251e.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 5 of 23 figure 2. 100-pin tqfp (top view) top view 100-pin tqfp 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc i/o 11l i/o 12l i/o 16l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 15l gnd i/o 13l i/o 14l a 1r a 2r a 3r a 4r nc nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l i/o 10l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 16r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r oe r r/w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c0241e/cy7c0251e i/o 8l i/o 17l i/o 8r i/o 17r r/w l [7] [6] pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 11/12l a 0r ?a 11/12r address i/o 0l ?i/o 15/17l i/o 0r ?i/o 15/17r data bus input/output sem l sem r semaphore enable ub l ub r upper byte select lb l lb r lower byte select int l int r interrupt flag busy l [8] busy r [8] busy flag m/s master or slave select v cc power gnd ground notes 6. a 12l on the cy7c025e/cy7c0251e. 7. a 12r on the cy7c025e/cy7c0251e. 8. busy is an output in master mode and an input in slave mode.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 6 of 23 architecture the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e consist of an array of 4 k words of 16/18 bits each and 8 k words of 16/18 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e have an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the r/w pin (see figure 7 ) or the ce pin (see figure 8 ). required inputs for non-contention operations are summarized in ta b l e 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data is valid on the port t ddd after the data is presen ted on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user of the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (fff for the cy7c024e/cy7c0241e, 1fff for the cy7c025e/cy7c0251e) is the mailbox for the right port and the second-highest memory location (ffe for the cy7c024e/cy7c0241e, 1ffe for the cy7c025e/cy7c0251e) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox . the message is user-defined. each port can read the other po rt?s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and thus resettin g the interrupt to it. if your application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2 on page 8 . busy the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e provide on-chip arbitration to resolve simultaneous memory location access (contentio n). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port definitely gains permission to the location, but which one is not predictable. busy is asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this allows the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ). otherwise, the slave chip may begin a write cycle durin g a contention si tuation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c024e/cy7c0241e and cy7c025e/cy7c0251e provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for tsop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was succe ssful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other addre ss pins have no effect.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 7 of 23 when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an av ailable semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if t he left port now relinquishes control by writing a one to the semapho re, the semaphore is set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port immediately owns the semaphore as soon as the left port releases it. table 3 on page 8 shows sample semaphore operations. when reading a semaphore, all 16/18 data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. table 1. non-contending read/write inputs outputs operation ce r/w oe ub lb sem i/o 0 ? i/o 7 [9] i/o 8 ? i/o 15 [10] h x x x x h high z high z deselected: power-down x x x h h h high z high z deselected: power-down l l x l h h high z data in write to upper byte only l l x h l h data in high z write to lower byte only l l x l l h data in data in write to both bytes l h l l h h high z data out read upper byte only l h l h l h data out high z read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed notes 9. i/o 0 ?i/o 8 on the cy7c0241e/cy7c0251e. 10. i/o 9 ?i/o 17 on the cy7c0241e/cy7c0251e.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 8 of 23 table 2. interrupt operation example (assumes busy l =busy r =high) [11] function left port right port r/w l ce l oe l a 0 l ?11 l int l r/w r ce r oe r a 0r?11r int r set right int r flag l l x (1)fff x x x x x l [12] reset right int r flag x x x x x x l l (1)fff h [13] set left int l flag x x x x l [13] llx(1)ffex reset left int l flag x l l (1)ffe h [12] xxx x x table 3. semaphore operation example function i/o 0 ? i/o 15/17 left i/o 0 ? i/o 15/17 right status no action 1 1 semaphore-free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no ch ange. right side has no write access to semaphore. left port writes 1 to semaphore 1 0 r ight port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore-free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore-free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore-free notes 11. a 0l?12l and a 0r?12r , 1fff/1ffe for the cy7c025e/cy7c0251e. 12. if busy l =l, then no change. 13. if busy r =l, then no change.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 9 of 23 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. [14] storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............. ............... ............... ?55 c to +125 c supply voltage to ground potenti al ...............?0.3 v to +7.0 v dc voltage applied to outputs in high z state ...............................................?0.5 v to +7.0 v dc input voltage [15] ......................................?0.5 v to +7.0 v output current into outputs (low) .............................. 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5 v ? 10% industrial ?40 c to +85 c 5 v ? 10% electrical characteristics over the operating range parameter description test conditions ?15 ?25 ?55 unit min typ max min typ max min typ max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? ? 2.4 ? ? 2.4 ? ? v v ol output low voltage v cc = min, i ol = 4.0 ma ? ? 0.4 ? ? 0.4 ? ? 0.4 v v ih input high voltage 2.2 ? ? 2.2 ? ? 2.2 ? ? v v il input low voltage ? ? 0.8 ? ? 0.8 ? ? 0.8 v i ix input leakage current gnd ? v i ? v cc ?10 ? +10 ?10 ? +10 ?10 ? +10 ? a i oz output leakage current output disabled, gnd ? v o ? v cc ?10 ? +10 ?10 ? +10 ?10 ? +10 ? a i cc operating current v cc = max, i out = 0 ma, outputs disabled commercial ? 190 285 ? 170 250 ? 150 230 ma industrial ? 215 305 ? 180 290 ? 180 290 i sb1 standby current (both ports ttl levels) ce l and ce r ? v ih , f = f max [16] commercial ? 50 70 ? 40 60 ? 20 50 ma industrial ? 65 95 ? 55 80 ? 55 80 i sb2 standby current (one port ttl level) ce l or ce r ? v ih , f = f max [16] commercial ? 120 180 ? 100 150 ? 75 135 ma industrial ? 135 205 ? 120 175 ? 120 175 i sb3 standby current (both ports cmos levels) both ports ce and ce r ? v cc ? 0.2 v, v in ? v cc ? 0.2 v or v in ? 0.2 v, f = 0 [16] commercial ? 0.05 0.5 ? 0.05 0.50 ? 0.05 0.50 ma industrial ? 0.05 0.5 ? 0.05 0.50 ? 0.05 0.50 i sb4 standby current (both ports cmos levels) one port ce l or ce r ? v cc ? 0.2 v, v in ?? v cc ? 0.2 v or v in ? 0.2 v, active port outputs, f = f max [16] commercial ? 110 160 ? 90 130 ? 70 120 ma industrial ? 125 175 ? 110 150 ? 110 150 notes 14. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 15. pulse width < 20 ns. 16. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 10 of 23 data retention mode the cy7c024e/cy7c0241e is designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules insure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v. 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power up and power down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (4.5 v). capacitance parameter [17] description test conditions max unit c in input capacitance t a = 25 c , f = 1 mhz, v cc = 5.0 v 10 pf c out output capacitance 10 pf figure 3. ac test loads and waveforms 3.0 v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 893 ? 5 v output r2 = 347 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay(load 3) c= 30pf output load (load 2) r1 = 893 ? r2 = 347 ? 5 v output c= 5pf r th =250 ? ? ? [18] max unit icc dr1 at vcc dr = 2 v 1.5 ma data retention mode 4.5 v 4.5 v v cc ? ? 2.0 v v cc to v cc ? 0.2 v v cc ce t rc v ih note 17. tested initially and after any design or proc ess changes that may affect these parameters. 18. ce = v cc , v in = gnd to v cc , t a = 25 ? c. this parameter is guaranteed but not tested.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 11 of 23 switching characteristics over the operating range parameter [19] description ?15 ?25 ?55 unit min max min max min max read cycle t rc read cycle time 15 ? 25 ? 55 ? ns t aa address to data valid ? 15 ? 25 ? 55 ns t oha output hold from address change 3 ? 3 ? 3 ? ns t ace [20] ce low to data valid ? 15 ? 25 ? 55 ns t doe oe low to data valid ? 10 ? 13 ? 25 ns t lzoe [21, 22, 23] oe low to low z 3 ? 3 ? 3 ? ns t hzoe [21, 22, 23] oe high to high z ? 10 ? 15 ? 25 ns t lzce [21, 22, 23] ce low to low z 3 ? 3 ? 3 ? ns t hzce [21, 22, 23] ce high to high z ? 10 ? 15 ? 25 ns t pu [23] ce low to power-up 0 ? 0 ? 0 ? ns t pd [23] ce high to power-down ? 15 ? 25 ? 55 ns t abe [20] byte enable access time ? 15 ? 25 ? 55 ns write cycle t wc write cycle time 15 ? 25 ? 55 ? ns t sce [20] ce low to write end 12 ? 20 ? 35 ? ns t aw address setup to write end 12 ? 20 ? 35 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa [24] address setup to write start 0 ? 0 ? 0 ? ns t pwe write pulse width 12 ? 20 ? 35 ? ns t sd data setup to write end 10 ? 15 ? 20 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe [25, 26] r/w low to high z ? 10 ? 15 ? 25 ns t lzwe [25, 26] r/w high to low z 3 ? 3 ? 3 ? ns t wdd [27] write pulse to data delay ? 30 ? 50 ? 70 ns t ddd [27] write data valid to read data valid ?25?35 ?45ns notes 19. test conditions assume signal tr ansition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 20. to access ram, ce =l, ub =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 21. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 22. test conditions used are load 3. 23. this parameter is guaranteed but not tested. 24. to access ram, ce =l, ub =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 25. test conditions used are load 3. 26. this parameter is guaranteed but not tested. 27. for information on port-to-port delay through ram cells from writing port to reading port, refer to figure 11 on page 16 .
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 12 of 23 busy timing [28] t bla busy low from address match ? 15 ? 20 ? 45 ns t bha busy high from address mismatch ?15?20 ?40ns t blc busy low from ce low ? 15 ? 20 ? 40 ns t bhc busy high from ce high ?15?20 ?35ns t ps port setup for priority 5 ? 5 ? 5 ? ns t wb r/w high after busy (slave) 0 ? 0 ? 0 ? ns t wh r/w high after busy high (slave) 13 ? 20 ? 40 ? ns t bdd [29] busy high to data valid ? note 29 note 29 note 29 ns interrupt timing [28] t ins int set time ?15?20 ?30ns t inr int reset time ?15?20 ?30ns semaphore timing t sop sem flag update pulse (oe or sem )10 ? 12 ? 20 ? ns t swrd sem flag write to read time 5 ? 10 ? 15 ? ns t sps sem flag contention window 5 ? 10 ? 15 ? ns t saa sem address access time ? 15 25 ? 55 ns switching characteristics (continued) over the operating range parameter [19] description ?15 ?25 ?55 unit min max min max min max notes 28. test conditions used are load 2. 29. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual).
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 13 of 23 switching waveforms notes 30. r/w is high for read cycles. 31. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 32. oe = v il . 33. address valid prior to or coincident with ce transition low. 34. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha figure 4. read cycle no. 1 (either port address access) [30, 31, 32] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current figure 5. read cycle no. 2 (either port ce /oe access) [30, 33, 34] ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce figure 6. read cycle no. 3 (either port) [30, 32, 33, 34]
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 14 of 23 notes 35. r/w must be high during all address transitions. 36. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 37. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at t he end of write cycle. 38. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 39. to access ram, ce = v il , sem = v ih . 40. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 41. transition is measured 500 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and n ot 100% tested. 42. during this period, the i/o pins are in the out put state, and input signals must not be applied. 43. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe figure 7. write cycle no. 1: r/w controlled timing [35, 36, 37, 38 ] [41] [41] [38] [39,40] note 42 note 42 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa figure 8. write cycle no. 2: ce controlled timing [35, 36, 37, 43] [39,40]
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 15 of 23 notes 44. ce = high for the duration of the above timing (both write and read cycle). 45. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 46. semaphores are reset (available to both ports) at cycle start. 47. if t sps is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable . switching waveforms (continued) t sop t aa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 figure 9. semaphore read after write timing, either side [44] match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r figure 10. timing diagra m of semaphore contention [45, 46, 47]
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 16 of 23 switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l figure 11. timing diagram of read with busy (m/s =high) [48] t pwe r/w busy t wb t wh figure 12. write timing with busy input (m/s =low) note 48. ce l = ce r = low.
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 17 of 23 note 49. if t ps is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side busy is asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r figure 13. busy timing diagram no.1 (ce arbitration) [49] ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: figure 14. busy timing diag ram no.2 (address arbitration) [49] left address valid first:
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 18 of 23 figure 15. interrupt timing diagrams notes 50. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 51. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write fff (1fff cy7c025) t wc right side clears int r : t ha read fff t rc t inr write ffe (1ffe cy7c025) t wc right side sets int l : left side sets int r : left side clears int l : read ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (1fff cy7c025) (1ffe cy7c025) [50] [51] [51] [51] [50] [51]
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 19 of 23 ordering information ordering code definitions 4 k 16 dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c024e-15axc a100 100-pin tqfp (pb-free) commercial 25 cy7c024e-25axc a100 100-pin tqfp (pb-free) commercial cy7c024e-25axi a100 100-pin tqfp (pb-free) industrial 55 cy7c024e-55axc a100 100-pin tqfp (pb-free) commercial 8 k 16 dual-port sram speed (ns) ordering code package name package type operating range 25 cy7c025e-25axc a100 100-pin tqfp (pb-free) commercial cy7c025e-25axi a100 100-pin tqfp (pb-free) industrial 55 cy7c025e-55axc a100 100-pin tqfp (pb-free) commercial 4 k 18 dual-port sram speed (ns) ordering code package name package type operating range 25 cy7c0241e-25axc a100 100-pin tqfp (pb-free) commercial 8 k 18 dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c0251e-15axc a100 100-pin tqfp (pb-free) commercial temperature range: x = c or i c = commercial; i = industrial pb-free package type: a = 100-pin tqfp speed: xx = 15 ns or 25 ns or 55 ns die revision data width: x = blank or 1 blank = 16; 1 = 18 density: 02x = 024 or 025 024 = 4-kbit; 025 = 8-kbit technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy - xx x 7 02x a x x e
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 20 of 23 package diagrams figure 16. 100-pin tqfp (14 14 1. 4 mm) a100sa package outline, 51-85048 51-85048 *h
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 21 of 23 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tqfp thin quad flat pack symbol unit of measure c degree celsius mhz megahertz ? a microampere ma milliampere ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy7c024e/cy7c0241e cy7c025e/cy7c0251e document number: 001-62932 rev. *e page 22 of 23 document history page document title: cy7c024e/cy7c0241e/cy7c025e/cy7c0251e, 4 k 16/18 and 8 k 16/18 dual-port static ram with sem, int, busy document number: 001-62932 rev. ecn no. orig. of change submission date description of change ** 2975554 rame 07/09/2010 new data sheet. *a 3056347 admu 10/28/2010 updated ?selection guide? on page 1: for speed bin -25: typical operating current(ma) changed from 180 to 170, typical standby current for isb1 (ma) changed from 45 to 40 for speed bin -55: typical operating current(ma) changed from 180 to 150, typical standby current for isb1 (ma) changed from 45 to 20. updated ?electrical characteristics? on page 9: the values for the speed bins -25 and -55 have been put into separate columns. the values for commercial parts have been modified for the following parameters: (no degradation of spec). operating current icc: ?180(typ) / 275 (max)? changed to ?170(typ) / 250(max) for speed bin -25? and ?150(typ) / 230(max) for speed bin -55? standby current isb1 (both ports ttl levels): ?45(typ) / 65(max)? changed to ?40(typ) / 60(max) for speed bin -25?, an d ?20(typ) / 50(max) for speed bin -55? standby current isb2 (one port ttl leve l) : ?110(typ) / 160(max)? changed to ?100(typ) / 150(max) for speed bin -25?, and ?75(typ) / 135(max) for speed bin -55? standby current isb4 (both ports cmos levels) : ?100(typ) / 140(max)? changed to ?90(typ) / 130(max) for speed bin -25?, and ?70(typ) / 120(max) for speed bin -55? updated ?4 k 18 dual-port sram? on page 19: removed part cy7c0241e - 55axi from ordering information. *b 3247559 admu 05/04/2011 removed vil min rating for all speed bins. updated ordering code definition details. updated package diagrams . *c 3864478 admu 01/10/2013 updated ordering information (updated part numbers). updated package diagrams : spec 51-85048 ? changed revision from *e to *g. *d 4075480 admu 07/24/2013 updated logic block diagram . updated pin configurations . updated in new template. completing sunset review. *e 4093991 admu 08/13/2013 updated package diagrams : spec 51-85048 ? changed revision from *g to *h. added units of measure .
document number: 001-62932 rev. *e revised august 13, 2013 page 23 of 23 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c024e/cy7c0241e cy7c025e/cy7c0251e ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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